This invention relates to a wafer exposure method adopting a step and repeat exposure method of a projection system, particularly a reduction projection system and an apparatus for carrying out the same.
With the progress of high integration LSI techniques, the importance of microlithography is increasing. The precision of microlithography greatly depends upon the performance of the exposure apparatus. Recently, the performance of the exposure apparatus has been strikingly improved, and step and repeat exposure apparatus of projection type, particularly reduction projection type, has been developed and is regarded to be an effective apparatus for lithography of line widths of the order of 1 .mu.m.
FIG. 1 shows the construction of a well-known step and repeat exposure apparatus. Referring to FIG. 1, to the top of a stage 1 which is movable in X- and Y-direction, is secured a wafer chuck 2 for securing a wafer to the stage 1. Above the stage 1, an optical column 3 including an optical system for reducing mask patterns is disposed. The optical column 3 is provided near the edge of its top with two marks 4a and 4b for being aligned with alignment marks of a mask to be described later. Right above the optical column 3, a light source 5 is disposed at a predetermined distance therefrom. Further, the optical column 3 is provided with an alignment system 6 on its side wall. The alignment system 6 includes a body 7 provided at the bottom with marks 8a and 8b for being aligned with the alignment marks of the mask to be described later and microscopes 9a and 9b provided on top of the body 7 for observing the state of alignment with the marks 8a and 8b with the alignment marks of the wafer. In the alignment system 6 of this kind, a mirror or a half mirror may be provided between the marks 8a and 8b and the microscopes 9a and 9b, and by the agency of this mirror or half mirror an alignment monitor 10 for observing the state of alignment between the marks 8a and 8b and the alignment marks of the alignment mask of wafer. The side of the stage 1 and the side of the optical column 3 are provided with marks 11a and 11b for effecting alignment of the two in the Y-direction.
Now, the method of wafer exposure with the reduction projection type step and repeat exposure apparatus described above will be described. The mask 12 is aligned with the optical column 3 by aligning the alignment marks 13a and 13b provided on a mask 12 having a desired mask pattern with the marks 4a and 4b provided on the optical column 3 near the edge of its top. With the reduction projection exposure system described above, the mask pattern of the mask 12 is projected on a reduced scale on a wafer. Therefore, with the reduction of the mask pattern the out-of-alignment between the mask 12 and optical column 3 is also reduced, and thus alignment departure from the alignment between the mask 12 and optical system 3 gives rise to no problem.
After the wafer 14 is secured to the wafer chuck 2, alignment between the wafer 14 and alignment system 6 is effected. More particularly, alignment marks 15a and 15b provided on the wafer 14 are aligned to the marks 8a and 8b of the main body 7 by moving the wafer 14 while observing it with the microscopes 9a and 9b or the alignment monitor 10. The alignment system 6 is secured to the optical column 3 at a predetermined position thereof, and thus the wafer 14 is indirectly aligned to the optical column 3 and mask 4.
After the alignment between the wafer 12 and alignment system 6 has been completed, the stage 1 is moved in the Y-direction along a rail (not shown) to effect alignment between the stage 1 and optical system 3 such that the wafer 14 is positioned directly beneath the optical column 3 as shown by double dot and bar line in FIG. 1. The alignment between the stage 1 and optical column 3 in the Y-direction may be automatically effected with a laser interferometer by making use of the mark 11a of the stage 1 and the mark 11b of the optical column.
After the alignment between the mask 12 and wafer 14 has been obtained, the step and repeat process is effected by moving the wafer 14 in the X- and Y-directions. For every step, light is projected from the light source 5 to illuminate the mask 12, and a reduced-scale pattern 16 of the mask pattern of the mask 12 is repeatedly projected on the wafer 14 as shown in FIG. 2.
After the exposure is ended, the stage 1 is returned to the initial position (i.e., the position at which the alignment between the wafer 14 and alignment system 6 has been effected), and then the wafer is replaced with a new one. Usually, the mask has one or more chip mask patterns, and the number of patterns 16 projected onto the wafer 14 is thus the product of the number of the chips of the mask and the number of times of repeat.
With the step and repeat exposure system as described above, with which the area of the wafer 14 on which light is projected in one shot (i.e., pattern 16) is small, the resolution can be revolutionally improved, compared to a one-to-one projection system.
However, the step and repeat exposure system as described above has the following drawbacks.
As in the case of a one-to-one projection system, it is difficult to expose such that the size of the chip pattern will be within a given tolerance over the entire area of the wafer 14. For example, even if the same mask is used for exposure, a chip pattern of 1.0 .mu.m may be obtained at the center of the wafer 14 while a chip pattern of 1.3 .mu.m may be obtained at the periphery of the wafer 14. This may be attributed to the following reason. When the resist film is rotation-coated onto the wafer 14 by a spinner, the thickness of a resist film 17 on the wafer 14 generally becomes thicker toward the periphery of the wafer 14, as shown in FIG. 3, although this depends on the viscosity of the resist, the rotational frequency of the wafer 14, and so on. For this reason, the resist image may differ from place to place. In addition to the nonuniformity of the thickness of the resist film, the nonuniformity of the resist image may also be attributed to changes in the developing characteristics. The width of the chip pattern is also affected by changes in the degree of side etching which is, in turn, caused by changes in the etching characteristics or thickness of the material to be etched. However, with respect to the etching characteristics, etching methods which do not cause side etching at all or which cause only slight side etching are already available, such as reactive ion etching. Therefore, if such an etching method is adopted, changes in the width of the chip pattern after etching need not be considered. However, the problem of changes in the size of the chip pattern which are attributable to the nonuniformity of the thickness of the resist film remains unsolved.